kernel

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clk

clock_source v9.0

Parameters clockFrequency 100000000 clockFrequencyKnown true

  

Software Assignments (none)

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cpu

altera_nios2 v9.0

Parameters userDefinedSettings setting_showUnpublishedSettings false setting_showInternalSettings false setting_shadowRegisterSetsPresent false setting_preciseSlaveAccessErrorException false setting_preciseIllegalMemAccessException false setting_preciseDivisionErrorException false setting_performanceCounter false setting_perfCounterWidth _32 setting_numShadowRegisterSets 1 setting_illegalMemAccessDetection false setting_illegalInstructionsTrap false setting_fullWaveformSignals false setting_extraExceptionInfo false setting_exportPCB false setting_eicPresent false setting_debugSimGen false setting_clearXBitsLDNonBypass true setting_branchPredictionType Automatic setting_bit31BypassDCache true setting_bhtPtrSz _8 setting_bhtIndexPcOnly false setting_avalonDebugPortPresent false setting_autoAssignNumShadowRegisterSets true setting_alwaysEncrypt true setting_allowFullAddressRange false setting_activateTrace true setting_activateTestEndChecker false setting_activateMonitors true setting_activateModelChecker false setting_HDLSimCachesCleared true setting_HBreakTest false resetSlave epcs.epcs_control_port resetOffset 0 muldiv_multiplierType EmbeddedMulFast muldiv_divider false mpu_useLimit false mpu_numOfInstRegion 8 mpu_numOfDataRegion 8 mpu_minInstRegionSize _12 mpu_minDataRegionSize _12 mpu_enabled false mmu_uitlbNumEntries _4 mmu_udtlbNumEntries _6 mmu_tlbPtrSz _7 mmu_tlbNumWays _16 mmu_processIDNumBits _8 mmu_enabled false mmu_autoAssignTlbPtrSz true mmu_TLBMissExcSlave mmu_TLBMissExcOffset 0 manuallyAssignCpuID false impl Fast icache_size _4096 icache_ramBlockType Automatic icache_numTCIM _0 icache_burstType None exceptionSlave sdram.s1 exceptionOffset 32 debug_triggerArming true debug_level Level1 debug_jtagInstanceID 0 debug_embeddedPLL true debug_debugReqSignals false debug_assignJtagInstanceID false debug_OCIOnchipTrace _128 dcache_size _2048 dcache_ramBlockType Automatic dcache_omitDataMaster false dcache_numTCDM _0 dcache_lineSize _32 dcache_bursts false cpuReset false cpuID 0 clockFrequency 100000000 breakSlave cpu.jtag_debug_module breakOffset 32

  

Software Assignments CPU_IMPLEMENTATION "fast" CPU_FREQ 100000000u ICACHE_LINE_SIZE 32 ICACHE_LINE_SIZE_LOG2 5 ICACHE_SIZE 4096 DCACHE_LINE_SIZE 32 DCACHE_LINE_SIZE_LOG2 5 DCACHE_SIZE 2048 INITDA_SUPPORTED FLUSHDA_SUPPORTED HAS_JMPI_INSTRUCTION EXCEPTION_ADDR 0x1000020 RESET_ADDR 0x0 BREAK_ADDR 0x1020 HAS_DEBUG_STUB HAS_DEBUG_CORE 1 CPU_ID_SIZE 1 CPU_ID_VALUE 0x0 HARDWARE_DIVIDE_PRESENT 0 HARDWARE_MULTIPLY_PRESENT 1 HARDWARE_MULX_PRESENT 0 INST_ADDR_WIDTH 25 DATA_ADDR_WIDTH 25

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sdram

altera_avalon_new_sdram_controller v9.0

Parameters TAC 5.5 TMRD 3 TRCD 20.0 TRFC 70.0 TRP 20.0 TWR 14.0 casLatency 3 clockRate 100000000 columnWidth 8 dataWidth 16 generateSimulationModel true initNOPDelay 0.0 initRefreshCommands 2 masteredTristateBridgeSlave model custom numberOfBanks 4 numberOfChipSelects 1 pinsSharedViaTriState false powerUpDelay 100.0 refreshPeriod 15.625 registerDataIn true rowWidth 12 size 8388608

  

Software Assignments REGISTER_DATA_IN 1 SIM_MODEL_BASE 1 SDRAM_DATA_WIDTH 16 SDRAM_ADDR_WIDTH 22 SDRAM_ROW_WIDTH 12 SDRAM_COL_WIDTH 8 SDRAM_NUM_CHIPSELECTS 1 SDRAM_NUM_BANKS 4 REFRESH_PERIOD 15.625 POWERUP_DELAY 100.0 CAS_LATENCY 3 T_RFC 70.0 T_RP 20.0 T_MRD 3 T_RCD 20.0 T_AC 5.5 T_WR 14.0 INIT_REFRESH_COMMANDS 2 INIT_NOP_DELAY 0.0 SHARED_DATA 0 STARVATION_INDICATOR 0 TRISTATE_BRIDGE_SLAVE "" IS_INITIALIZED 1 SDRAM_BANK_WIDTH 2 CONTENTS_INFO ""

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epcs

altera_avalon_epcs_flash_controller v9.0

Parameters autoSelectASMIAtom true useASMIAtom true

  

Software Assignments REGISTER_OFFSET 512

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sysid

altera_avalon_sysid v9.0

Parameters id 157960459 timestamp 1308202234

  

Software Assignments ID 157960459u TIMESTAMP 1308202234u

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jtag_uart

altera_avalon_jtag_uart v9.0

Parameters allowMultipleConnections false hubInstanceID 0 readBufferDepth 64 readIRQThreshold 8 simInputCharacterStream simInteractiveOptions INTERACTIVE_ASCII_OUTPUT useRegistersForReadBuffer false useRegistersForWriteBuffer false writeBufferDepth 64 writeIRQThreshold 8

  

Software Assignments WRITE_DEPTH 64 READ_DEPTH 64 WRITE_THRESHOLD 8 READ_THRESHOLD 8

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led

altera_avalon_pio v9.0

Parameters bitClearingEdgeCapReg false bitModifyingOutReg false captureEdge false clockRate 100000000 direction Output edgeType RISING generateIRQ false irqType LEVEL resetValue 0 simDoTestBenchWiring false simDrivenValue 0 width 4

  

Software Assignments DO_TEST_BENCH_WIRING 0 DRIVEN_SIM_VALUE 0x0 HAS_TRI 0 HAS_OUT 1 HAS_IN 0 CAPTURE 0 BIT_CLEARING_EDGE_REGISTER 0 BIT_MODIFYING_OUTPUT_REGISTER 0 DATA_WIDTH 4 RESET_VALUE 0x0 EDGE_TYPE "NONE" IRQ_TYPE "NONE" FREQ 100000000u